A Low-Power Command-Driven SAR ADC for Implantable Cardiac Pacemakers

Most conventional ADCs sample the signal at a fixed sampling rate $\left(f_{s}\right)$, leading to either loss of the peak information of the cardiac signal (for low $f_{\mathrm{s}}$) or unnecessary redundant data and power consumption (for high $f_{\text {s }}$) when used to convert ECG signals. This paper presents a command-driven SAR ADC aiming to support those adaptive- $f_{\text {s }}$ algorithms for low-energy and high-quality acquisition of ECG signals. Upon receiving a quantization command pulse (QCP), the proposed asynchronous SAR ADC converts the signal tracked on its capacitive DAC (CDAC) into digits immediately without a specific sampling phase. Once the conversion completes, the ADC turns into the default tracking mode with zero power consumption and waits for the next QCP. A low-leakage rising-edge delay cell is also proposed to reduce power consumption of the SAR logic circuit further. Fabricated in a $180-\mathrm{nm}$ CMOS process with an active area of $0.087 \mathrm{~mm}^{2}$, the ADC achieves 59.4-dB SNDR and 76.1-dB SFDR at 1-kSPS $f_{\mathrm{s}}$ while consuming 227 nW under 2 V supply voltage. When the ADC is used to sample the ECG signal with an adaptive $2-f_{\text {s }}$ strategy (100 SPS or 1 kSPS), the compression factor is 7.6, and the ADC power consumption is only 38 nW, achieving a power saving factor of 83%.