Towards EKV3.0 Model for Bulk-Driven IC Design in 65 nm CMOS Technology

The paper addresses an ongoing research in the field of ultra low-power and ultra low-voltage IC design and compact modelling of MOS transistors in nanoscale CMOS technologies. We discuss the current state-of-the-art of analog bulk-driven integrated circuit (BD IC) design in modern sub-l00 nm CMOS processes, and we also discuss the obvious need for accurate MOS device modelling in such operating conditions. Based on our initial research carried out mainly using 130 nm CMOS, we decided to migrate to 65 nm CMOS process. Naturally, this introduces a whole new level of difficulties for analog designers, as well as for developers of bulk-driven simulation models. We describe the development and application of EKV3.0 transistor model in ultra low-voltage / low-power analog bulk-driven IC design in 65 nm CMOS process.