A High Accuracy and Low Power Consumption ASIC Based on Multi Voltage Threshold Method for Positron Emission Tomography Application

A 36-channel application-specific integrated circuit (ASIC) is proposed for the application of time-of-flight positron emission tomography (ToF-PET). The multiple voltage threshold (MVT) method designs the whole system. This ToF-PET ASIC integrates high-performance hysteresis comparators, high-accuracy time-to-digital converters (TDCs), and an advanced read-out circuit. A delay compensation circuit in hysteresis comparators improves the problem of inconsistent delay in comparator output under different threshold voltages, enhancing the accuracy of the effective signal. After being fast triggered by hysteresis comparators, the cyclic vernier TDC generates coarse, medium, and fine time stamps and records the time over the threshold. All these time stamps, which build up the 48-bit time data, will be stored in dual-loop first-in, first-out (FIFO) memory. The FIFO memory preserves data integrity and alleviates the dead time of the TDC. The ASIC is manufactured using a standard CMOS $55-\mathrm{nm}$ process with a core area of $1 \times 5 \mathbf{~ m m}^{2}$ and a whole chip power consumption of 310.43 mW. The system achieves ultra-high time resolution with 10.3 ps and a wide quantization range of 1200 s.