A Fully-Integrated Backscatter Modulation System with High Image Rejection and Near Zero Power Wake-up Receiver Offset Cancellation

This paper presents a design of a spectral efficient backscatter modulation system with integrated Wilkinson power divider (WPD) and novel wake-up receiver calibration technique. This structure consumes $44.5 \mu \mathrm{~W}$ and occupies an effective area of $0.77 \times 0.88 \mathrm{~mm}^{2}$ which achieves about 1,000 times footprint reduction compared to off-chip WPD implementations, making it applicable in implantable biomedical devices. The innovative RF front-end, featured a quadrature load combination using a capacitive path and a short circuit path, along with a symmetric multiplexer-based single sideband intermediate frequency mixer, achieves high image rejection for enhanced spectral efficiency. The pseudo-differential wake-up receiver that employs an offset cancellation technique presents $\mathbf{\sim 2 0} \mathrm{dB}$ enhanced sensitivity. This work is verified in standard $0.18-\mu \mathrm{m}$ CMOS technology. Silicon measurement results demonstrate a 31.4 dB image rejection ratio and -39.9 dBm receiver sensitivity. Then, data recovery in a software-defined radio (SDR) setup is carried out to demonstrate its functionality in real-time transmission.