A 1.01μV_rms, 16.5bit ECG Acquisition IC with Embedded DC-Servo-Loop and Multi Channel Discharge Dynamic Comparator

This paper proposes a high-precision ECG acquisition analog front-end (AFE) with a capacitively-coupled chopper instrumentation amplifier (CCIA), a LPF and a noise-shaping delta sigma ADC. The CCIA employs an embedded DC-servo loop to reduce input-referred noise (IRN) and incorporates self-regulating bias and common-mode replication techniques to enhance the common-mode rejection ratio (CMRR). The input stage of the delta sigma ADC utilizes the substrate-biasing bootstrap switch to mitigate body effects, thereby improving linearity and signal-to-noise ratio. The output stage utilizes a multi channel discharge dynamic comparator with a preamplifier stage that suppresses kickback noise. The CCIA achieved 1.01 $\mu V_{r m s}$ IRN from 0.5 to 150 Hz and 96.54 dB CMRR. The ADC achieved 16.5 effective number of bit (ENOB) within a 1 k bandwidth. The AFE is implemented in a $0.18 \mu \mathrm{~m}$ CMOS process and consumes $33.4 \mu W$ from a 1.8 V supply.