HAF: A High PE Utilization Spike-Based CNN Accelerator with Adaptive Input Compression and Forward-Based Data Flow

As artificial intelligence applications expand in various domains, addressing challenges such as reducing memory size and latency of recognition has become crucial. This paper proposes HAF, a spike-based convolutional neural network accelerator that leverages the sparsity of the input signal to achieve data compression and computation acceleration. To reduce power consumption while classifying the CIFAR-10 dataset with VGG16, the proposed design skips computations for zero inputs. This will decrease the number of processing elements required to process zero-valued inputs within the accelerator and reduce $\mathbf{7 5. 5 4 \%}$ of input SRAM access. The TSMC 40nm library performance achieves 51.31 TOPS/W power efficiency and 1859.71 GOPS equivalent average throughput in 97% input sparsity ratio.

Authors

Institutions

Publication Details

Published
2024-10-24
DOI
https://doi.org/10.1109/biocas61083.2024.10798278
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

HAF: A High PE Utilization Spike-Based CNN Accelerator with Adaptive Input Compression and Forward-Based Data Flow

Kuan-Pei Lee, Kea‐Tiong Tang, Zhouyu Wu
CCD and CMOS Imaging Sensors
article

HAF: A High PE Utilization Spike-Based CNN Accelerator with Adaptive Input Compression and Forward-Based Data Flow

Kuan-Pei Lee, Kea‐Tiong Tang, Zhouyu Wu
article en

Abstract

As artificial intelligence applications expand in various domains, addressing challenges such as reducing memory size and latency of recognition has become crucial. This paper proposes HAF, a spike-based convolutional neural network accelerator that leverages the sparsity of the input signal to achieve data compression and computation acceleration. To reduce power consumption while classifying the CIFAR-10 dataset with VGG16, the proposed design skips computations for zero inputs. This will decrease the number of processing elements required to process zero-valued inputs within the accelerator and reduce $\mathbf{7 5. 5 4 \%}$ of input SRAM access. The TSMC 40nm library performance achieves 51.31 TOPS/W power efficiency and 1859.71 GOPS equivalent average throughput in 97% input sparsity ratio.

National Tsing Hua University (TW)
Affordable and clean energy
Openalex Percentile: Top 78%
CCD and CMOS Imaging Sensors
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.