An ultra-miniaturized Neural Recording μASIC for the NeuroBus Implant

Advances in technology and circuit design contributed to the development of implantable neural interfaces. Electronics for these devices are often sealed in bulky ceramic capsules and implanted at a distance from the electrodes, requiring long multiwired cables. This paper presents an ultraminiaturized neural recording $\mu \mathrm{ASIC}$ for a new implant concept called NeuroBus. The $50 \mu \mathrm{~m}$ thin $\mu \mathrm{ASIC}$ with an area of only $0.13 \mathrm{~mm}^{2}$ can be embedded directly on the electrode substrate, allowing signal digitization close to the electrode. The small size of the $\mu$ ASIC results in a low bending stiffness of the implant, which is necessary for good structural biocompatibility. A lightweight digital interface allows readout of several $\mu$ ASICs. Inter-ASIC communication and neural recorder performance have been validated, achieving a bit error rate (BER) better than $10^{-10}$ with a confidence level of 99.7%, and an input referred noise of $2.6 \mu \mathrm{~V}_{\text {rms }}$ and $6.1 \mu \mathrm{~V}_{\text {rms }}$ for the local field potential (LFP) and action potential (AP) bands, respectively. The typical power consumption of a $\mu \mathrm{ASIC}$ with a 1 pF load on the data line is $60 \mu \mathrm{~W}$.