A 96dB DR 3.1GΩ Input Impedance CT-DT ΔΣ Readout Frontend with Level-Crossing Input Range Enhancement for Neural Recordings

This paper proposes a neural recording frontend with a level crossing (LC) style DR-enhancing loop, featuring fast transient response and a wide input range. A dual-Gm input stage together with a differential input single-ended output TIA is exploited, enabling energy efficient LC event detection. The LC capacitive DAC generates a voltage that follows the input, enhancing the DR. A current mode second order CT-DT $\Delta \mathbf{\Sigma}$ modulator follows the dual-Gm stage in the main signal path for data conversion. Prior to the CT-integrator, a common mode current sinking circuit is used to improve the linearity. Designed and simulated in a 55 nm CMOS technology, the proposed frontend supports ± 400mV DC suppression thanks to the DR enhancement. It also achieves a 96 dB DR, a 64.3dB SNDR within the $0.1-10 \mathrm{kHz}$ bandwidth and a $3.1 \mathrm{G} \Omega Z_{\mathrm{in}}$, making it suitable for simultaneously recoding of ECG, EEG and vagus nerve signals.

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Publication Details

Published
2024-10-24
DOI
https://doi.org/10.1109/biocas61083.2024.10798349
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
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article

A 96dB DR 3.1GΩ Input Impedance CT-DT ΔΣ Readout Frontend with Level-Crossing Input Range Enhancement for Neural Recordings

Shuang Song, Zhaonan Lu, Menglian Zhao, Tian Yang et al.
CCD and CMOS Imaging Sensors
article

A 96dB DR 3.1GΩ Input Impedance CT-DT ΔΣ Readout Frontend with Level-Crossing Input Range Enhancement for Neural Recordings

Shuang Song, Zhaonan Lu, Menglian Zhao, Tian Yang, Zhichao Tan, Shiwei Wang, Mengyu Li, Yiqi Chen, Yongpeng Cheng
article en

Abstract

This paper proposes a neural recording frontend with a level crossing (LC) style DR-enhancing loop, featuring fast transient response and a wide input range. A dual-Gm input stage together with a differential input single-ended output TIA is exploited, enabling energy efficient LC event detection. The LC capacitive DAC generates a voltage that follows the input, enhancing the DR. A current mode second order CT-DT $\Delta \mathbf{\Sigma}$ modulator follows the dual-Gm stage in the main signal path for data conversion. Prior to the CT-integrator, a common mode current sinking circuit is used to improve the linearity. Designed and simulated in a 55 nm CMOS technology, the proposed frontend supports ± 400mV DC suppression thanks to the DR enhancement. It also achieves a 96 dB DR, a 64.3dB SNDR within the $0.1-10 \mathrm{kHz}$ bandwidth and a $3.1 \mathrm{G} \Omega Z_{\mathrm{in}}$, making it suitable for simultaneously recoding of ECG, EEG and vagus nerve signals.

Zhejiang University (CN), University of Edinburgh (GB)
Openalex Percentile: Top 78%
CCD and CMOS Imaging Sensors
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