Characterization of near-interface traps in thermally oxidized and NO-annealed SiO2/4H-SiC metal-oxide-semiconductor capacitors by transient capacitance measurement

The quality of the SiO2/4H-SiC interface is critical for enhancing the performance of 4H-SiC metal–oxide–semiconductor field effect transistor devices. This research primarily concentrates on characterizing near-interface traps (NITs) in the SiO2/4H-SiC metal–oxide–semiconductor (MOS) capacitor using transient capacitance (C–t) measurements. Two types of samples were analyzed: thermally oxidized SiO2/4H-SiC MOS capacitors with (sample OX) and without (sample NO) NO post-oxidation annealing. It was found that the measurement voltage in C–t measurements significantly affects the electrical response of NITs, which has not received substantial attention in previous reports. By carefully selecting the measurement voltage, the maximum distance that carriers can tunnel into SiO2 from 4H-SiC can be assessed. Under the stress condition of maintaining a gate voltage of 20 V for 100 s, the maximum tunneling distances were determined to be 1.6 nm for sample OX and 1.4 nm for sample NO. Additionally, the concentrations of active NITs in both samples were examined. The results provide direct evidence that NO annealing significantly reduces active NITs, particularly those located farther from the interface.