An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC

Abstract This paper proposes an 8-bit synthesizable SAR ADC with inverter-cell-based capacitive digital-to-analog converters (CDACs). An inverter-cell-based capacitor is proposed by connecting the supply and ground ports of the inverter cells together but leaving them floated to suppress the voltage dependence to be suitable for employment in an ADC with moderate resolution. Furthermore, an inverter-cell-based analog switch is proposed to be employed in S/H and CDAC to achieve a fully standard-cell-based design without any custom-designed cells. The prototype is fabricated in a 65 nm standard CMOS process occupying 0.19 mm 2 . With a Nyquist input, the SFDR and SNDR reach 53.6 dB and 46.2 dB at 2.92 MS/s respectively without calibration. The power consumption is 425 $${\mu }$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>μ</mml:mi> </mml:math> W from a 1.2 V supply, which leads to the Walden FoM of 0.86 pJ/conv.-step.