Leveraging Machine Learning for Enhanced Automation in VLSI Layout Design: Optimizing Performance and Efficiency

The complexity of Very-Large-Scale Integration (VLSI) design continues to grow with the increasing demand for highperformance and low-power electronic devices.Traditional layout generation methods often rely on manual processes that are time-intensive and prone to human error.This paper investigates the integration of machine learning techniques, specifically supervised and reinforcement learning algorithms, to automate layout generation in VLSI.The framework optimizes spatial arrangement and connectivity while reducing power consumption and enhancing processing efficiency.The proposed approach demonstrates significant improvements, including a 25% reduction in wire length (from 200 m to 150 m), a 21.6% decrease in signal delay (from 12.5 ns to 9.8 ns) and a 26.5% reduction in power dissipation (from 10.2 mW to 7.5 mW).Furthermore, placement time is reduced by an impressive 68.75% (from 8.0 hours to 2.5 hours), highlighting the system's ability to accelerate the design process.This study validates the robustness of the proposed machine learning-driven framework across diverse design constraints, achieving up to 95.6% placement efficiency in tight area scenarios and maintaining adaptability under high routing complexity.These results establish machine learning as a transformative tool for enhancing performance and efficiency in VLSI layout design, offering a scalable and reliable solution for the evolving challenges in electronic design automation.