Single event upset and mitigation technique in JLTFET based RF mixer

• Designed a 20 nm independent gate Junctionless Tunnel FET (IGJLTFET) and constructed an IGJLTFET based RF mixer using Verilog-A approach. • Achieved a 1-dB compression point (P1dB) of 16 dBm to assess mixer linearity. • Evaluated the performance with metrics like conversion gain, noise figure, and power dissipation. • Emulated a heavy ion strike at the transistor's drain to observe single event upset (SEU), plotting the intermediate frequency (IF) spectrum. • Mitigated SEU effects by 95.5% using RC components, maintaining similar gain and power consumption with only a slight increase in noise figure and power dissipation after radiation hardening. This work deals with the study of single event effect (SEE) on RF mixer along with the mitigation technique. A 20 nm independent gate Junctionless Tunnel FET JLTFET (IGJLTFET) was first designed and based on its I d -V g characteristics; RF mixer circuit was constructed using Verilog A code. The RF mixer was operated at a frequency of 95 GHz with local oscillator frequency (LO) of 100 GHz. The output spectrum consisting of sum and difference of input signals are obtained. The linearity of the mixer was determined using the metric,1-dB compression point (P1dB) with a value of 16 dBm. The performance of the circuit is assessed using the parameters, conversion gain (G C ), noise figure (NF), power dissipated and power consumed. The heavy ion strike is emulated from current source model which was made to strike at the drain of the transistor. Single event upset (SEU) is noted during the ion strike and the spectrum of intermediate frequency (IF) is plotted. To recover from SEU, mitigation is carried out with RC components which eliminates the single event upset to a greater extent of 95.5 %. It could be noted that RF mixer shows almost the same gain and power consumption after radiation hardening with a slight increase in NF and power dissipation.