Energy Efficient Approximate Multiplier for Image Processing Applications

• This manuscript presents two novel imprecise 4:2 compressors used for implementing 8 × 8 dadda multipliers. These compressors incorporate an input reordering circuit that enhances accuracy while reducing hardware complexity. • On average, the proposed multipliers achieve a 20.19 % reduction in power-delay product (PDP), with error rates of approximately 26.67 % and 74.66 % compared to an accurate multiplier. • Additionally, these multipliers demonstrate superior circuit performance optimization, maintaining an average mean structural similarity index measure (MSSIM) of 97.59 % across various image processing applications. • Proposed design 1 exhibits higher MSSIM values, indicating superior accuracy compared to both other designs and the proposed design 2. • The suggested approximation multiplier architecture provides an optimal trade-off between circuit design and accuracy, surpassing most other approximate multipliers in performance. Approximate multipliers have paved the way for high-speed and energy-efficient applications with reduction in area, power consumption and delay. This is generally achieved with a slight compromise in computational accuracy. This study presents two novel imprecise 4:2 compressors which are used for implementing 8 × 8 Dadda multipliers. These compressors incorporate an input reordering circuit which increases the accuracy as well as reduces the hardware complexity at the same time. The efficiency of these approximate multipliers, constructed using the novel compressors, is extensively evaluated against different implementation and accuracy parameters. On average, the proposed multipliers achieve a 20.19 % reduction in power delay product (PDP), with error rates of approximately 26.67 % and 74.66 % compared to an accurate multiplier. Additionally, they demonstrate superior circuit performance optimization as compared to the state-of-the-art approximate multipliers. Simulation results in terms of Mean Structural Similarity Index Measure (MSSIM) for different image processing applications, show that the proposed multipliers maintain an average structural similarity of 97.59 % compared to exact multipliers.

Authors

Publication Details

Journal
Results in Engineering
Published
2024-12-22
DOI
https://doi.org/10.1016/j.rineng.2024.103798
Citations
7
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
1.46
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article

Energy Efficient Approximate Multiplier for Image Processing Applications

Ashis Kumar Chakraborty, Jagannadha Naidu K, S. Balamurugan, Akash Kumar Vruddhula et al.
7 citations
Results in Engineering
Low-power high-performance VLSI design
1.46
article

Energy Efficient Approximate Multiplier for Image Processing Applications

Ashis Kumar Chakraborty, Jagannadha Naidu K, S. Balamurugan, Akash Kumar Vruddhula, Vishal Pranao Amarnath Kumar
article en
7 citations

Abstract

• This manuscript presents two novel imprecise 4:2 compressors used for implementing 8 × 8 dadda multipliers. These compressors incorporate an input reordering circuit that enhances accuracy while reducing hardware complexity. • On average, the proposed multipliers achieve a 20.19 % reduction in power-delay product (PDP), with error rates of approximately 26.67 % and 74.66 % compared to an accurate multiplier. • Additionally, these multipliers demonstrate superior circuit performance optimization, maintaining an average mean structural similarity index measure (MSSIM) of 97.59 % across various image processing applications. • Proposed design 1 exhibits higher MSSIM values, indicating superior accuracy compared to both other designs and the proposed design 2. • The suggested approximation multiplier architecture provides an optimal trade-off between circuit design and accuracy, surpassing most other approximate multipliers in performance. Approximate multipliers have paved the way for high-speed and energy-efficient applications with reduction in area, power consumption and delay. This is generally achieved with a slight compromise in computational accuracy. This study presents two novel imprecise 4:2 compressors which are used for implementing 8 × 8 Dadda multipliers. These compressors incorporate an input reordering circuit which increases the accuracy as well as reduces the hardware complexity at the same time. The efficiency of these approximate multipliers, constructed using the novel compressors, is extensively evaluated against different implementation and accuracy parameters. On average, the proposed multipliers achieve a 20.19 % reduction in power delay product (PDP), with error rates of approximately 26.67 % and 74.66 % compared to an accurate multiplier. Additionally, they demonstrate superior circuit performance optimization as compared to the state-of-the-art approximate multipliers. Simulation results in terms of Mean Structural Similarity Index Measure (MSSIM) for different image processing applications, show that the proposed multipliers maintain an average structural similarity of 97.59 % compared to exact multipliers.

Results in EngineeringVol. 25
Affordable and clean energy
Openalex Percentile: Top 17%
Low-power high-performance VLSI design
1.46
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