Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality

This paper utilizes the digital integrated circuit testing model to compute the test yield curve of future wafers and explore the influence of test guardband (TGB) on quality and yield. With the passage of three years since the COVID-19 pandemic disrupted semiconductor production lines, the semiconductor manufacturing industry still faces chip shortages. Although initiatives such as the CHIPS and Science Act in the United States have helped stabilize chip supply chains, manufacturers still face inventory shortages and delayed deliveries. Moreover, the backwardness and inaccuracy of semiconductor test equipment have led to a decline in both test yield and wafer quality, resulting in reduced shipments. Therefore, to mitigate yield losses and enhance the test yield and shipment volume of semiconductor products, this paper proposes a diverse test method (DTM) to improve test outcomes through the alteration of the testing strategy and TGB adjustment. Furthermore, according to the wafer estimation table published in the IEEE International Roadmap for Devices and Systems (2023), the proposed DTM can effectively enhance the test yield of wafers and improve the testing capabilities of ATE testers (automatic test equipment). Consequently, suppliers can stabilize the chip supply chain and enhance their companies’ profits and reputation by improving chip test yield.