The Automation of the Verification Process of Hardware IP Registers

The technology progress witnessed in the past few decades would have not been possible without the hardware support, which nowadays is most of the time a System on Chip (SoC) composed of multiple Hardware Intellectual Properties (IPs). The SoC market faces a number of challenges, including among them the time required to bring a concept to market availability. Frequently, this challenge is handled by developing configurable IPs, which can have their configurations changed depending on the requirements. Because the configurability is achieved predominantly through registers, the number of registers inside the IP and the complexity of the verification process escalate with the number of configurations. The Universal Verification Methodology (UVM) offers the UVM Register Abstraction Layer (UVM RAL) library for the management and the access of the registers, which has a series of benefits that are accompanied by the cost of its development. This paper addresses the automation of the UVM RAL generation with the help of a Python script that accepts as input a file in xlsx format with the registers description and generates the UVM register model. The register model has been integrated in a verification environment alongside the Device under Test (DUT) for which it was generated, in order to validate the functionality of the script.