XTEA Brute-Force Cracker for FPGA in HLS and HDL

This work presents a study comparing Extended Tiny Encryption Algorithm (XTEA) brute-force cracker C++/hlsand Verilog/HDL implementations on FPGA. The HDL-based implementation outperformed the HLS-based implementation by a factor of 2.8, and it also demonstrated exceptionally low total power dissipation compared to both CPU and GPU implementations.

Authors

George-Vlăduț Popescu (ORCID: https://orcid.org/0000-0002-7962-1875)
Călin Bîră (ORCID: https://orcid.org/0000-0001-7111-6324)
Costin-Emanuel Vasile (ORCID: https://orcid.org/0009-0004-2573-0509)

Institutions

Universitatea Națională de Știință și Tehnologie Politehnica București (RO)

Publication Details

Published: 2024-11-07
DOI: https://doi.org/10.1109/isetc63109.2024.10797331
Primary Topic: Embedded Systems Design Techniques
Type: article
Field-Weighted Citation Impact: 0.00

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article

XTEA Brute-Force Cracker for FPGA in HLS and HDL

George-Vlăduț Popescu, Călin Bîră, Costin-Emanuel Vasile

Nov 7, 2024

Embedded Systems Design Techniques

article

XTEA Brute-Force Cracker for FPGA in HLS and HDL

George-Vlăduț Popescu, Călin Bîră, Costin-Emanuel Vasile

November 7, 2024article en

Abstract

This work presents a study comparing Extended Tiny Encryption Algorithm (XTEA) brute-force cracker C++/hlsand Verilog/HDL implementations on FPGA. The HDL-based implementation outperformed the HLS-based implementation by a factor of 2.8, and it also demonstrated exceptionally low total power dissipation compared to both CPU and GPU implementations.

Universitatea Națională de Știință și Tehnologie Politehnica București (RO)

Openalex Percentile: Top 75%

Embedded Systems Design Techniques

DOI Source OpenAlex

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XTEA Brute-Force Cracker for FPGA in HLS and HDL — George-Vlăduț Popescu, Călin Bîră, et al. · (2024) | TGRS Research Map | TGRS