Feedback-enabled low-latency adiabatic quantum-flux-parametron logic using a mixed clocking scheme

Abstract Adiabatic quantum-flux-parametron (AQFP) logic stands as an energy-efficient superconductor logic family relying on ac excitations. Though a four-phase clocking scheme has been commonly applied to excite and clock AQFP circuits, the cost of multiple sources and long between-stage latency (a quarter clock cycle) remain unsatisfactory. These drawbacks are more severe for sequential logics, where feedback loops require both down-flow and reverse-flow AQFP gates, necessitating extra buffers and imposing a limit on operating depth at the same time. To overcome these restrictions, in this paper, we introduce a novel mixed clocking scheme for low-latency AQFP logic circuits allowing feedback loops. In particular, the down-flow part of the AQFP circuit is excited by an ac current through delay-lines, which can reduce the latency from input to output stages. Meanwhile, the reverse-flow part is clocked by 2 other ac currents with 90° phase difference to reduce the buffering gates. The proposed clocking scheme is first applied to a fundamental logic circuit, confirming correct functionality and low-latency operations for diverse feedback conditions. For experimental validation, we design and fabricate a 3-bit AQFP counter using the proposed clocking scheme based on an on-chip clock splitter. The circuit is examined at 4 GHz under 4.2 K temperature, where we obtain desired operations and wide excitation margins.