The Impact of Varying the High-Temperature Post-Deposition Anneal Time or Temperature Ramp Rates on ALD-SiO₂/4H-SiC Interfaces

A Post-deposition annealing (PDA) study on atomic layer deposited (ALD)-SiO2/4H-SiC Metal-oxide semiconductor capacitors (MOSCAPs) is presented in this paper. This paper reports that varying the annealing time in conventional PDA (in Nitrous oxide or forming gas) and in forming gas rapid thermal annealing (RTA) PDA does not affect the electrical parameters of the MOS interface. Varying the annealing temperature for forming gas quartz PDA does not affect the electrical parameters either. Flatband voltage, hysteresis, and frequency dispersion of the MOS interface individually all had a positive correlation against the temperature ramp rate, while the annealing time and temperature were kept constant. This result subsequently led to a thermal budget investigation of all PDAs, revealing that thermal budget affects the flatband voltage and hysteresis of the SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>/4H-SiC MOS interface.