Development of a 500V/0.3kA DC Circuit Breaker Testbed Using a DC Chopper Energized Capacitor Bank

DC fault interruption technology is essential for the protection and mitigation of current faults in the modern power grid, with the DC Circuit Breaker (DC CB) being the core component of such protection systems. One of the primary steps in validating and demonstrating the technical feasibility of a DC CB topology is prototyping and testing it under quasi-grid-like conditions. In this article, an LVDC (500kV/0.3kA) testbed is proposed to mimic the necessary current/voltage stress across the DC interrupter under consideration. An artificial current fault is generated using a capacitor bank, energized through rectifier and chopper circuits. Before fault instigation, the voltage across the DC test apparatus is kept 12% higher and drops to the rated DC CB voltage after the DC CB interrupts the fault, thereby applying appropriate dielectric stress. A simplified control mechanism has been developed and simulated in PSCAD/EMTDC software, validating the working principle of the test-bed model.

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Published
2024-11-10
DOI
https://doi.org/10.1109/icepe-st61894.2024.10792624
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
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article

Development of a 500V/0.3kA DC Circuit Breaker Testbed Using a DC Chopper Energized Capacitor Bank

Y. Kwak, Muhammad Usman, K. H. Park, Woosung Choi et al.
Silicon Carbide Semiconductor Technologies
article

Development of a 500V/0.3kA DC Circuit Breaker Testbed Using a DC Chopper Energized Capacitor Bank

Y. Kwak, Muhammad Usman, K. H. Park, Woosung Choi, Bang-Wook Lee, Illoong Kwon
article en

Abstract

DC fault interruption technology is essential for the protection and mitigation of current faults in the modern power grid, with the DC Circuit Breaker (DC CB) being the core component of such protection systems. One of the primary steps in validating and demonstrating the technical feasibility of a DC CB topology is prototyping and testing it under quasi-grid-like conditions. In this article, an LVDC (500kV/0.3kA) testbed is proposed to mimic the necessary current/voltage stress across the DC interrupter under consideration. An artificial current fault is generated using a capacitor bank, energized through rectifier and chopper circuits. Before fault instigation, the voltage across the DC test apparatus is kept 12% higher and drops to the rated DC CB voltage after the DC CB interrupts the fault, thereby applying appropriate dielectric stress. A simplified control mechanism has been developed and simulated in PSCAD/EMTDC software, validating the working principle of the test-bed model.

Hanyang University (KR)
Affordable and clean energy
Openalex Percentile: Top 78%
Silicon Carbide Semiconductor Technologies
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