Development of a 500V/0.3kA DC Circuit Breaker Testbed Using a DC Chopper Energized Capacitor Bank
DC fault interruption technology is essential for the protection and mitigation of current faults in the modern power grid, with the DC Circuit Breaker (DC CB) being the core component of such protection systems. One of the primary steps in validating and demonstrating the technical feasibility of a DC CB topology is prototyping and testing it under quasi-grid-like conditions. In this article, an LVDC (500kV/0.3kA) testbed is proposed to mimic the necessary current/voltage stress across the DC interrupter under consideration. An artificial current fault is generated using a capacitor bank, energized through rectifier and chopper circuits. Before fault instigation, the voltage across the DC test apparatus is kept 12% higher and drops to the rated DC CB voltage after the DC CB interrupts the fault, thereby applying appropriate dielectric stress. A simplified control mechanism has been developed and simulated in PSCAD/EMTDC software, validating the working principle of the test-bed model.
Authors
- Y. Kwak (ORCID: https://orcid.org/0000-0003-2902-3428)
- Muhammad Usman (ORCID: https://orcid.org/0000-0003-3728-082X)
- K. H. Park
- Woosung Choi (ORCID: https://orcid.org/0000-0002-7001-3099)
- Bang-Wook Lee (ORCID: https://orcid.org/0000-0001-9975-8812)
- Illoong Kwon (ORCID: https://orcid.org/0000-0002-4888-4058)
Institutions
- Hanyang University (KR)
Publication Details
- Published
- 2024-11-10
- DOI
- https://doi.org/10.1109/icepe-st61894.2024.10792624
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00