Understanding Inter-Chip Oscillations in Paralleled SiC MOSFETs

This study analyzes self-excited inter-chip oscillations in paralleled SiC MOSFETs. Initial measurements and simulations demonstrating these oscillations are presented. A novel stability analysis approach based on Modified Nodal Analysis (MNA) is then proposed, offering significantly greater speed and flexibility compared to conventional methods. This method allows for the detailed investigation of asymmetric layout and chip parameters. Simulation and measurement results are subsequently provided to demonstrate the dependence of oscillation amplitude on bias conditions, including DC-link voltage, load current, and switching speed.