A power‐saving control voltage‐retention circuit for fast‐locking phase‐locked loops with sleep mode

Abstract This study proposes a voltage‐retention circuit (VRC) for a low‐power phase‐locked loop (PLL) designed for mobile interfaces. The PLL, incorporating the proposed scheme, supports the sleep mode to achieve low power consumption and fast switching between the sleep and active modes. To facilitate rapid switching between these modes, the proposed VRC stores the filter information from the previous input during sleep mode, ensuring quick settling upon reactivation. The VRC comprises a resistor‐steering digital‐to‐analog converter (DAC), a comparator, and a counter. During the active mode, the circuit adjusts the DAC using the comparator and counter to track the loop‐filter voltage, and it holds the tracked voltage value during the sleep mode. The proposed circuit, designed using a 65‐nm CMOS process, demonstrates 54% improved settling time compared to conventional circuits. Additionally, it reduces power consumption during sleep mode by 88%.