A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS

This work presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.