FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders
This work proposes an integrated framework for accuracy and logic synthesis (LS) estimation of approximate adders (FALSAx). It represents a versatile and robust framework designed to estimate the accuracy, power, and area of various approximate adders (AxAs) for any input width (W) and K bits of approximation using machine learning (ML) models. FALSAx facilitates performance predictions and optimization for different AxAs configurations through meticulously curated datasets and ML-driven analysis. The framework’s capability to automatically generate Pareto fronts from estimated values aids in identifying optimal trade-offs among crucial metrics, providing essential insights for circuit design and optimization. The FALSAx includes four internal frameworks: FrAQ, PILSE, and FELSE, which estimates dynamic power, total leakage power, and area, with frequency variations automatically, and the FALED dataset of the FALSAx. As a case study, this work analyzed 16 types of AxAs on FALSAx: AMA-V, AxPPA, COPY, TRUNC, ETA, LOA, HOERAA, LDCA, LZTA, HEAA, M-HEAA, HERLOA, M-HERLOA, HOAANED, OLOCA, and SETA. The rigorous analysis provided by FALSAx revealed that HERLOA, M-HERLOA, M-HEAA, and AxPPA demonstrated superior accuracy metrics such as SSIM, NCC, MAE, and MRE. Furthermore, power analysis showed that AxPPA exhibited the best power efficiency for lower approximation bits (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K \leq 3$ </tex-math></inline-formula>). At the same time, gate-free adders like COPY, TRUNC, AMA-V, LDCA, and LZTA were more power-efficient for higher approximation bits (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K \gt 3$ </tex-math></inline-formula>). Area estimations indicated that AxPPA maintained competitive efficiency for lower approximation bits (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K \leq 5$ </tex-math></inline-formula>), while TRUNC and LDCA were more efficient for higher bits (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K \gt 5$ </tex-math></inline-formula>).
Authors
- Rafael Soares (ORCID: https://orcid.org/0000-0001-9493-7272)
- Morgana Macedo Azevedo da Rosa (ORCID: https://orcid.org/0000-0001-9582-9011)
- Eloisa Barros
- Eduardo Costa (ORCID: https://orcid.org/0009-0009-2731-8864)
- Leonardo Antonietti
- Rodrigo Lopes
Institutions
- Universidade Católica de Pelotas (BR)
- Universidade Federal de Pelotas (BR)
Publication Details
- Journal
- IEEE Transactions on Circuits and Systems I Regular Papers
- Published
- 2024-12-19
- DOI
- https://doi.org/10.1109/tcsi.2024.3511383
- Citations
- 2
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.42
Funders
- Coordenação de Aperfeiçoamento de Pessoal de Nível Superior