Proposed Optimized Hardware Implementation for the S-box of the PRESENT Algorithm Using Combinational Logic Circuits

The lightweight block cipher PRESENT has been standardized by ISO/IEC 29192-2:2012 and TCVN 12854-2:2020. It is a lightweight block cipher with a block size of 64 bits and key sizes of either 80 or 128 bits. For lightweight block ciphers commonly deployed in resource-constrained embedded and IoT devices, resource optimization is a top priority. The S-box, as the only nonlinear component, plays a crucial role in ensuring the security of the cryptographic algorithm by providing resistance against nonlinear and differential attacks. The S-box also consumes the most resources compared to other components of the algorithm, making the optimization of the S-box implementation essential for minimizing the overall resource usage of the algorithm. The S-box of the PRESENT algorithm is used in many other block cipher algorithms. By surveying existing research on PRESENT implementations and analyzing S-box deployment methods based on combinational logic circuits, this paper proposes new architectures for implementing S-boxes using the lowest resource-consuming logic gates, such as 2-input NAND gates, 2-input NOR gates, and NOT gates. The results demonstrate that the proposed methods achieve reduced resources compared to other designs