The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter

In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics. The CIS with the proposed 10/11-bit hybrid SS-ADC was fabricated using a 110 nm 1-poly 4-metal CIS process. The measurement results showed that dark random noise was reduced by 8% in low light when using the proposed hybrid SS-ADC, compared with the existing 10-bit ADC. Additionally, in the case of high brightness, when using a 10-bit resolution, the dynamic power consumption decreased by approximately 31%, compared to the 11-bit ADC. The total power consumption is 3.9 mW at 15 fps when the analog, pixel, and digital supply voltages are 3.3 V, 3.3 V, and 1.5 V, respectively.