IMPLEMENTED RECONFIGURABLE CACHE MEMORY ARCHITECTURE BASED ON 32-BITS MIPS PROCESSOR

This work presents the design of a reconfigurable cache memory utilizing a 32-bit MIPS processor, implemented through the utilization of VHDL (Very high-speed IC Hardware Description Language). A comprehensive implementation of a 32-bit, single-cycle MIPS processor is presented in VHDL. This processor is capable of supporting 50 instructions, comprising 25-R-type, 16-I-type, and 9-J-type instructions. The processor incorporates a three-dimensional reconfigurable cache memory architecture, enabling the modification of cache memory size, cache organization (in terms of associativity), and cache block size. The reconfigurable cache memory concept proposes the use of multi-cache controller units to execute reconfiguration operations and ensure that all permitted cache memory sets can be utilized with varying levels of associativity. The design is built on an FPGA using the Xilinx ISE design suite, which is based on the hardware description language. To ensure that assess functionality of the proposed reconfigurable cache memory design for various reconfiguration scenarios, numerous assembly language programs have been developed and performed on the MIPS processor. The results validated the efficacy of the suggested reconfigurable cache memory concept and demonstrated its simulation using the Xilinx ISim simulator.