An improved direct digital synthesis technique for railway application

This paper represents a method for producing frequency modulated signals for railway application based on traditional direct digital synthesis. This method can save the storage space of the LUT (Look Up Tables), and generate high precision signals in limited resources of embedded devices such as FPGA (Field Programmable Gate Array). Two different widths look up compressed tables based on standard look up tables are built for constructing the digital signal. Applying the interpolation technique and making full use of symmetric and anti-symmetric characteristics of sinusoidal waves can also reduce the depth of the look up tables. The proposed technique is realized on low-cost FPGAs with smaller flash memory, actual performance during experimental validation is represented in this paper.

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Publication Details

Journal
IET conference proceedings.
Published
2024-12-01
DOI
https://doi.org/10.1049/icp.2024.4072
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
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article

An improved direct digital synthesis technique for railway application

Yi Chen, Cheng Yuan, Huachao Wang, Guoying Sun et al.
IET conference proceedings.
Embedded Systems Design Techniques
article

An improved direct digital synthesis technique for railway application

Yi Chen, Cheng Yuan, Huachao Wang, Guoying Sun, Guoqiao Ren, Zisheng Li
article en

Abstract

This paper represents a method for producing frequency modulated signals for railway application based on traditional direct digital synthesis. This method can save the storage space of the LUT (Look Up Tables), and generate high precision signals in limited resources of embedded devices such as FPGA (Field Programmable Gate Array). Two different widths look up compressed tables based on standard look up tables are built for constructing the digital signal. Applying the interpolation technique and making full use of symmetric and anti-symmetric characteristics of sinusoidal waves can also reduce the depth of the look up tables. The proposed technique is realized on low-cost FPGAs with smaller flash memory, actual performance during experimental validation is represented in this paper.

IET conference proceedings.Vol. 2024(20)
CRRC (China) (CN)
Openalex Percentile: Top 75%
Embedded Systems Design Techniques
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