CMOS Comparator Design using 90nm Technology

In many digital circuits the parameters gain and offset voltage are calculated. In our design of CMOS comparator with high performance using GPDK 90nm technology we optimize these parameters. The gain is calculated in AC analysis and also we measure area, delay, power dissipation, slew rate, rise time, fall time. The circuit is built by using PMOS and NMOS transistor with a body effect and we also measure mobility variation and channel length modulation based on the second order channel effects. A plot of gain and offset voltage also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 1.2V is measured using Cadence virtuoso.