Design of Delta-Sigma Modulators for Closed Loop Systems with Quantization and Saturation

This paper studies ΔΣ modulators for discrete-time closed loop systems. ΔΣ modulators have been originally developed as efficient analog-to-digital converters (ADCs). Recently, ΔΣ modulators are designed based on the characteristics of the system that uses the ΔΣ modulator. For example in a control system, quantization may degrade control performance due to quantization errors, while the input to any practical system is limited to a range. Then, the saturation of the control input may cause windup phenomena such as overshoots of the system outputs and instability of the control system. In this paper, we propose a design of ΔΣ modulators to mitigate the effects of quantization and saturation in a discrete-time closed loop system. We design the ΔΣ modulator to minimize the norm of the quantization error at the system output to reduce the effects of the quantization error under a stability condition to avoid the saturation of the input on the closed-loop system. Numerical examples are provided to see the effectiveness of our proposed design.