Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)

Abstract In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technology has been introduced. As the track height in conventional standard cells scales down to 3-track standard cell, the distance in-between the BPR metal and the bottom parasitic channel is required to be 13 nm or narrower. Consequently, a strong lateral electric-field, induced by the BPR, is applied to the substrate parasitic channel, resulting in a substrate leakage current. To address this issue, various materials for barrier/liner in the BPR structure are explored and evaluated using TCAD simulation. It turned out that the BPR-induced field effect was suppressed as the dielectric constant of the barrier material and the work function of TiN liner decreased. The proposed BPR structure demonstrates the potential to mitigate device leakage current without increasing the doping concentration in substrate.