Design of a Low-Power 4x4 Wallace Tree Multiplier Using Ripple Carry Adder at 10 MHz in 180nm CMOS Techology

The research focused on designing a low-power 4x4 Wallace Tree Multiplier for integration into wearable devices, driven by the growing prevalence of wearable technology and the demand for energy-efficient circuits. The use of the Wallace tree multiplier technique, which minimized partial products to reduce power consumption and multiplication delay, was proposed. The design employs the Wallace Tree multiplier technique, strategically minimizing partial products to curtail power consumption. Executed through the 180nm CMOS process, the design features a 4x4 bit configuration and operates with a supply voltage of 1.8 V, and its performance was assessed using Synopsys. A comparative analysis was conducted to evaluate the proposed multiplier against existing designs in terms of power consumption, measuring at 11.4480 µW at FF Corner, with 10 MHz as the operating at a frequency. This conspicuous enhancement in power efficiency underscores the substantial progress achieved by the proposed design, especially in the context of minimizing power consumption for applications in wearable technology