Innovative electro-structural integration approach defining large-area PMUT on TFT backplane for ultrasound imaging systems

We demonstrate an electro-structural integration approach to define piezoelectric micromachined ultrasound transducers (PMUT) on top of thin-film-transistor (TFT) backplanes for imaging applications, enabling large-area, low-cost transducer arrays. While the piezo stacks for these microelectromechanical structures (MEMS) are manufactured in a silicon foundry, the switches for element addressing are made separately using a standard TFT process, in a flat-panel-display fab. Cu/Ni/Sn microrings are processed on top of the piezo stack at wafer level, before a flip-chip assembly approach bonds a single thinned silicon die to the Ni/Au stack atop the TFT-on-glass die. The assembled devices are tested mechanically, electrically, and acoustically. A pulse-echo based 2D imaging demonstration is presented.

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Published
2024-09-22
DOI
https://doi.org/10.1109/uffc-js60046.2024.10793958
Primary Topic
Engineering Applied Research
Type
article
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article

Innovative electro-structural integration approach defining large-area PMUT on TFT backplane for ultrasound imaging systems

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Engineering Applied Research
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Innovative electro-structural integration approach defining large-area PMUT on TFT backplane for ultrasound imaging systems

Dominika Wysocka, Antonia Malainou, Robert Ukropec, Véronique Rochus, Xavier Rottenberg, Pieter Gijsenbergh, Florian De Roose, Raf Appeltans, Alessandro Stoppato, Zhiyuan Shen
article en

Abstract

We demonstrate an electro-structural integration approach to define piezoelectric micromachined ultrasound transducers (PMUT) on top of thin-film-transistor (TFT) backplanes for imaging applications, enabling large-area, low-cost transducer arrays. While the piezo stacks for these microelectromechanical structures (MEMS) are manufactured in a silicon foundry, the switches for element addressing are made separately using a standard TFT process, in a flat-panel-display fab. Cu/Ni/Sn microrings are processed on top of the piezo stack at wafer level, before a flip-chip assembly approach bonds a single thinned silicon die to the Ni/Au stack atop the TFT-on-glass die. The assembled devices are tested mechanically, electrically, and acoustically. A pulse-echo based 2D imaging demonstration is presented.

IMEC (BE)
Openalex Percentile: Top 73%
Engineering Applied Research
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