Hardware description language versus high-level synthesis for the FPGA implementation of ultrasound beamformers: a comparative analysis

The rapid advancement of ultrasound techniques necessitates highly adaptable, versatile, and efficient systems. Field-Programmable Gate Arrays (FPGAs) are frequently used for implementing reception beamformers, which are crucial for image quality. Traditional coding with hardware description language (HDL) is time-consuming and requires specialized expertise, leading to the exploration of high-level synthesis (HLS) as a potential solution. This paper presents a comparative analysis of HLS and HDL in the implementation of delay-and-sum (DAS) and filtered-delay-multiply-and-sum (FDMAS) beamformers on Intel Arria V FPGAs, which are integrated in the ULA-OP 256 research scanner. Both beamformers were developed using Intel Quartus, sharing a common HDL-designed data acquisition layer. The comparison is focused on the firmware development time assessed by source lines of code (SLOC), FPGA resource utilization and maximum clock frequency. The results demonstrate that HLS reduces the HDL SLOC by 70%; however, it consumes over 1.5 times more FPGA resources, and operates with a 20% lower clock frequency. Although both approaches were used to synthesize two parallel beamformers for comparison due to HLS resource constraints, optimal resource usage in HDL enables the synthesis of additional parallel beamformers, potentially doubling the FR and improving timing performance. Thus, while HLS serves as a valuable tool for rapid firmware development, HDL remains essential for applications with stringent performance and resource utilization requirements.