Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines

This paper introduces two new single-path and cascaded High-Resolution Digital Pulse Width Modulation (HRDPWM) architectures. The proposed single-path architecture uses fewer FPGA resources to achieve the same resolution as conventional dual-path architectures. Moreover, the generated HRDPWM signal is independent of the Place-And-Route (PAR) algorithm applied by the synthesis tool, as well as temperature and voltage variations. The proposed cascaded architecture can be used to increase the DPWM resolution without raising the system clock frequency or, alternatively, to reduce the FPGA system clock frequency (relaxing timing challenges) without lowering the resolution. Both architectures have been implemented and verified using a mid-range Artix-7 FPGA with both triangular and sawtooth carriers. A time resolution of 39 ps has been achieved for the cascaded HRDPWM architecture with a sawtooth carrier and a system clock of 400 MHz. Additionally, a GaN-based synchronous buck converter is designed and implemented to evaluate the performance of the proposed HRDPWM architectures in a real application. It is demonstrated that bothhldead time and duty cycle can be modified with high accuracy and resolution and updated twice per switching cycle.