Implementation of a Robust Chirplet Signal Decomposition Algorithm on FPGA-SoC Platform for Ultrasonic Flaw Detection

This research presents a robust chirplet decomposition algorithm designed for hardware implementation, specifically aimed at enhancing ultrasonic nondestructive testing and imaging. The study focuses on developing an algorithm and an FPGA hardware module that enable real-time chirplet decomposition, emphasizing increased processing speed while maintaining echo accuracy. A novel Maximum Likelihood Estimation (MLE)-based parameter estimation algorithm was developed to improve chirplet parameter estimation, enhancing both accuracy and convergence speed. This high-performance platform enables real-time ultrasonic imaging for flaw detection in steel specimens, demonstrating significant improvements in defect detection and characterization. The resultant platform has been tested against four alternative platforms to evaluate its effectiveness in enhancing execution times. Remarkably, when compared to similar embedded platforms, this speed-optimized platform achieves a 150-fold increase in processing speed, surpassing the next fastest embedded platform, the Teensy 4.0, which includes a Cortex-M7 processor operating at 600MHz. Additionally, when compared to an AMD Ryzen 7 3700X, this platform operates 6.6 times faster.