A 26–32-GHz CMOS Attenuator With Optimized Capacitive Compensation and High Linearity Enhancement

This article presents a 26–32-GHz 6-bit differential attenuator in the 40-nm CMOS process. This attenuator adopts an optimized cascade scheme that incorporates simplified T-type (ST-type), T-type, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Pi $ </tex-math></inline-formula>-type attenuator units. Driven by a complete analysis of the pole-zero pattern introduced by the compensation capacitor, the design achieves a state-of-art uncalibrated rms attenuation and phase error. This article further examines the influence of nonidealities of switches on frequency response and optimizes the switch size to expand bandwidth (BW). Moreover, this work analyzes the linearity of T-type and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Pi $ </tex-math></inline-formula>-type attenuation units using the EKV model, followed by techniques that ensure the high linearity of the overall attenuator through optimal cascading order of these units. The attenuator achieves a 31.5-dB attenuation range with 0.5-dB step and 8.5–9.5-dB insertion loss (IL) in a compact area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.54\times 0.23$ </tex-math></inline-formula> mm. The measured rms attenuation error remains below 0.23 dB without calibration and the phase error is less than 5.58°. The measured IP<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> in the reference state is better than 11.2 dBm across 26–32 GHz.