Advanced 3-D Packaging for Integrated 2-D PMUT Arrays and Front-End Circuits

This paper presents a novel 3D packaging technique for integrating large 2-D Piezoelectric Micromachined Ultrasonic Transducer (PMUT) arrays with front-end circuits using a hybrid approach. This method allows the separate fabrication of the MEMS and ASICs, offering increased design flexibility and improved production yield. The packaging process involves flip-chip bonding of a 2-D PMUT array to a Fan-Out Wafer-Level Package (FOWLP) containing front-end ASICs. A 64×64 PMUT array, operating at 2 MHz with 80% two-way bandwidth, was fabricated and connected to a FOWLP housing 4 dummy ASICs. These ASICs were designed to form a 64×4-element 1.5-D array by electrically connecting, in the elevation direction, two symmetric groups of 8 adjacent PMUT array elements. The resulting electro-acoustic module (EAM) was mounted on a rigid-flex PCB and integrated in a probe head. Electrical impedance and acoustic tests confirmed the reliability and repeatability of the 3D packaging technique.

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Publication Details

Published
2024-09-22
DOI
https://doi.org/10.1109/uffc-js60046.2024.10793875
Citations
2
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.42
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Advanced 3-D Packaging for Integrated 2-D PMUT Arrays and Front-End Circuits

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article

Advanced 3-D Packaging for Integrated 2-D PMUT Arrays and Front-End Circuits

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article en
2 citations

Abstract

This paper presents a novel 3D packaging technique for integrating large 2-D Piezoelectric Micromachined Ultrasonic Transducer (PMUT) arrays with front-end circuits using a hybrid approach. This method allows the separate fabrication of the MEMS and ASICs, offering increased design flexibility and improved production yield. The packaging process involves flip-chip bonding of a 2-D PMUT array to a Fan-Out Wafer-Level Package (FOWLP) containing front-end ASICs. A 64×64 PMUT array, operating at 2 MHz with 80% two-way bandwidth, was fabricated and connected to a FOWLP housing 4 dummy ASICs. These ASICs were designed to form a 64×4-element 1.5-D array by electrically connecting, in the elevation direction, two symmetric groups of 8 adjacent PMUT array elements. The resulting electro-acoustic module (EAM) was mounted on a rigid-flex PCB and integrated in a probe head. Electrical impedance and acoustic tests confirmed the reliability and repeatability of the 3D packaging technique.

Agency for Science, Technology and Research (SG), Roma Tre University (IT), Institute of Microelectronics (SG), STMicroelectronics (Italy) (IT), University of Florence (IT)
Affordable and clean energy
Openalex Percentile: Top 36%
3D IC and TSV technologies
0.42
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