Advanced 3-D Packaging for Integrated 2-D PMUT Arrays and Front-End Circuits
This paper presents a novel 3D packaging technique for integrating large 2-D Piezoelectric Micromachined Ultrasonic Transducer (PMUT) arrays with front-end circuits using a hybrid approach. This method allows the separate fabrication of the MEMS and ASICs, offering increased design flexibility and improved production yield. The packaging process involves flip-chip bonding of a 2-D PMUT array to a Fan-Out Wafer-Level Package (FOWLP) containing front-end ASICs. A 64×64 PMUT array, operating at 2 MHz with 80% two-way bandwidth, was fabricated and connected to a FOWLP housing 4 dummy ASICs. These ASICs were designed to form a 64×4-element 1.5-D array by electrically connecting, in the elevation direction, two symmetric groups of 8 adjacent PMUT array elements. The resulting electro-acoustic module (EAM) was mounted on a rigid-flex PCB and integrated in a probe head. Electrical impedance and acoustic tests confirmed the reliability and repeatability of the 3D packaging technique.
Authors
- Rahul Dutta (ORCID: https://orcid.org/0000-0001-5254-6994)
- Carlo Prelini
- Alessandro Stuart Savoia (ORCID: https://orcid.org/0000-0002-1111-7437)
- Mark Shaw
- Enrico Boni (ORCID: https://orcid.org/0000-0002-9899-8782)
- Piero Tortoli (ORCID: https://orcid.org/0000-0002-7984-3128)
- Alessandro Ramalli (ORCID: https://orcid.org/0000-0003-4358-3739)
- Monica La Mura (ORCID: https://orcid.org/0000-0001-8410-2511)
- Vempati Srinivasa Rao (ORCID: https://orcid.org/0000-0002-5616-0324)
- Domenico Giusti
- Mohammad Mahdi Dehghan Pir
- David Ho Soon
Institutions
- Agency for Science, Technology and Research (SG)
- Roma Tre University (IT)
- Institute of Microelectronics (SG)
- STMicroelectronics (Italy) (IT)
- University of Florence (IT)
Publication Details
- Published
- 2024-09-22
- DOI
- https://doi.org/10.1109/uffc-js60046.2024.10793875
- Citations
- 2
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.42