Design Oriented Dynamic-to-Steady Time Domain Model of CLLC Converter Considering Secondary Parasitic Capacitors

In order to improve the accuracy of CLLC converter design, a dynamic-to-steady time domain model of CLLC converter considering secondary parasitic capacitors is proposed in this paper. Based on the iteration of equivalent circuits, transient waveform can be obtained from the proposed model like circuit simulation, and the speed is much faster than that of the simulation software since the analytical solution has been derived. Experimental results show that the proposed model can substantially improve the accuracy of voltage gain calculation compared to existing time-domain models that does not consider the parasitic capacitance.