Discontinuous Pulse-Width Modulation with Naturally Balanced DC-Link Capacitor Voltages for Three-Phase Four-Level Inverters

Four-level inverters offer lower voltage strain and less current fluctuations than two- or three-level inverters, but suffer from more severe DC-link capacitor voltage imbalance issue. The existing pulse-width modulation (PWM) schemes with voltage balancing capability leads to significant increase of switching loss, which decreases the efficiency of the inverter. In this paper, four-level discontinuous PWM (4L-DPWM) is proposed to reduce the switching loss of four-level inverters, while achieving naturally balanced DC-link capacitor voltage. Firstly, the segmentation of subsector and sequence of switching-state are optimized in a four-level space-vector diagram. During each switching period, five vectors are employed to synthesizes the reference vector and clamp the switching state of one phase. Thus, switching times are reduced. Then, the voltage balancing constraints are considered while calculating the dwelling time of each vector, by which the DC-link capacitor voltage achieve natural balance. Finally, simulation verification confirm that the proposed 4L-DPWM strategy successfully balances the capacitor voltage while reducing switching loss.