3D Interconnect Inspection for Chiplet Packaging using White-light Scanning and Phase-Shifting Interferometry

This article presents white-light scanning interferometry (WSI) and multi-wavelength phase-shifting interferometry (MPSI) for advanced heterogeneous chip 3D bump inspection. First, 3D automated optical inspection (AOI) using oblique and coaxial methods is introduced. Specifically, scanning interferometry, a coaxial method, is described for its accurate measurement of 3D interconnects ranging from a few micrometers to several hundred micrometers. The second section details key features of interferometry technology, including multi-reflectance surface 3D measurement, a highspeed camera, a custom-made frame grabber, and a large field of view (FOV), followed by an explanation of the 3D inspection algorithm. Additionally, inspection results and 3D interconnect parameters such as bump height, bump coplanarity, and chip area warpage (CAW) are discussed to address the challenges of large form factor multi-chip packaging. A significant challenge is ensuring successful die bonding conditions before attaching the silicon die to the costly multi-chip package.

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Publication Details

Published
2024-11-12
DOI
https://doi.org/10.1109/paine62042.2024.10792698
Primary Topic
3D IC and TSV technologies
Type
article
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3D Interconnect Inspection for Chiplet Packaging using White-light Scanning and Phase-Shifting Interferometry

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3D IC and TSV technologies
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3D Interconnect Inspection for Chiplet Packaging using White-light Scanning and Phase-Shifting Interferometry

HyunMin Lee, Sangyoon Lee, Min‐Gu Kang, H. Song, Shahab Chitchian, S. H. Song
article en

Abstract

This article presents white-light scanning interferometry (WSI) and multi-wavelength phase-shifting interferometry (MPSI) for advanced heterogeneous chip 3D bump inspection. First, 3D automated optical inspection (AOI) using oblique and coaxial methods is introduced. Specifically, scanning interferometry, a coaxial method, is described for its accurate measurement of 3D interconnects ranging from a few micrometers to several hundred micrometers. The second section details key features of interferometry technology, including multi-reflectance surface 3D measurement, a highspeed camera, a custom-made frame grabber, and a large field of view (FOV), followed by an explanation of the 3D inspection algorithm. Additionally, inspection results and 3D interconnect parameters such as bump height, bump coplanarity, and chip area warpage (CAW) are discussed to address the challenges of large form factor multi-chip packaging. A significant challenge is ensuring successful die bonding conditions before attaching the silicon die to the costly multi-chip package.

Openalex Percentile: Top 79%
3D IC and TSV technologies
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