Mechanical Sample Preparation for Heterogeneous Integration(HI) Packaging
Sample preparation (S-prep) is important in the semiconductor devices as it aids in the removal of unwanted materials for failure analysis and hardware assurance. However, the significance of s-prep has often been underestimated in the research community. Without fully discussing the challenges associated with s-prep for the developed metrology, the feasibility of performing hardware assurance and failure analysis methodologies accurately is compromised. This problem exacerbates with the emergence of Heterogeneous Integration (HI) packaging, which encompasses complex challenges. This paper aims to underscore the importance of s-prep by comparing its applications in various failure analysis and hardware assurance scenarios. Subsequently, it will introduce different types of S-prep methods. Lastly, the S-prep methodology for HI packaging will be extensively detailed in this paper to highlight its difficulties in exposing certain features within HI packaging.
Authors
- Chengjie Xi
- Chris G. Richardson (ORCID: https://orcid.org/0000-0002-7641-7027)
- Nitin Varshney
- M Shafkat M Khan (ORCID: https://orcid.org/0000-0002-8532-8720)
- Aslam A. Khan (ORCID: https://orcid.org/0000-0002-8766-9692)
- Navid Asadizanjani (ORCID: https://orcid.org/0000-0003-3347-5072)
Institutions
- University of Florida (US)
- Allied Technology (United States) (US)
Publication Details
- Published
- 2024-11-12
- DOI
- https://doi.org/10.1109/paine62042.2024.10792771
- Citations
- 1
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.21