Physical Layout Extraction via Ion Milling based IC Delayering for Reverse Engineering Applications

Reverse engineering using physical inspection has gained prominence in recent times due to its ability to detect Hardware Trojans hiding within the physical layout of integrated circuits (ICs). This requires sophisticated IC delayering, simultaneously imaging each of its layers, and finally matching the corresponding images with the original Graphic Design System (GDS) files. In this study, we aim to meticulously perform IC delayering using broad beam ion milling, focusing on refining process parameters to ensure a smooth, flat surface. Following this, we propose the use of a Swin transformer based Generative Adversarial Network (GAN) to effectively segment out metal lines, vias, and backgrounds within standard noisy electron microscopy images.