Assuring the Cybersecurity of COTS Processors in Space Systems

The recent surge in the deployment of satellites in low Earth orbit has created a demand for affordable and dependable hardware solutions. Non-radiation hardened Commercial-Off-The-Shelf (COTS) hardware offers a costeffective and high-performance alternative to radiation-hardened components. However, COTS hardware is more vulnerable to radiation-induced faults, such as bit flips caused by single event upsets (SEUs). These faults can compromise system integrity and security, potentially jeopardizing both the system and the mission. To mitigate these risks, there is a growing interest in hardening existing COTS systems using software-based techniques. This approach requires a methodology to assess the efficacy of different software strategies. This paper addresses these challenges by evaluating several combinations of operating systems and software-based mitigation strategies through fault injection simulations. The study found that the use of a separation kernel in a bespoke operating system, Magnetite, based on the seL4 microkernel, along with components like the Memory Management Unit (MMU), Memory Protection Unit (MPU), and Watchdog Timer (WDT), proved effective in reducing the impact of SEUs on COTS hardware.

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Publication Details

Published
2024-11-12
DOI
https://doi.org/10.1109/paine62042.2024.10792785
Primary Topic
Distributed systems and fault tolerance
Type
article
Field-Weighted Citation Impact
0.00

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article

Assuring the Cybersecurity of COTS Processors in Space Systems

Keith Bergevin, Benjamin Nahill, P. Gogna, Richard Skowyra et al.
Distributed systems and fault tolerance
article

Assuring the Cybersecurity of COTS Processors in Space Systems

Keith Bergevin, Benjamin Nahill, P. Gogna, Richard Skowyra, Jeffery Lim, Michael Vai, Allan Nesathurai
article en

Abstract

The recent surge in the deployment of satellites in low Earth orbit has created a demand for affordable and dependable hardware solutions. Non-radiation hardened Commercial-Off-The-Shelf (COTS) hardware offers a costeffective and high-performance alternative to radiation-hardened components. However, COTS hardware is more vulnerable to radiation-induced faults, such as bit flips caused by single event upsets (SEUs). These faults can compromise system integrity and security, potentially jeopardizing both the system and the mission. To mitigate these risks, there is a growing interest in hardening existing COTS systems using software-based techniques. This approach requires a methodology to assess the efficacy of different software strategies. This paper addresses these challenges by evaluating several combinations of operating systems and software-based mitigation strategies through fault injection simulations. The study found that the use of a separation kernel in a bespoke operating system, Magnetite, based on the seL4 microkernel, along with components like the Memory Management Unit (MMU), Memory Protection Unit (MPU), and Watchdog Timer (WDT), proved effective in reducing the impact of SEUs on COTS hardware.

MIT Lincoln Laboratory (US), Massachusetts Institute of Technology (US)
Defense Microelectronics Activity
Openalex Percentile: Top 73%
Distributed systems and fault tolerance
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Assuring the Cybersecurity of COTS Processors in Space Systems — Keith Bergevin, Benjamin Nahill, et al. · (2024) | TGRS Research Map | TGRS