Pre-Silicon Side-Channel Analysis of AI/ML Systems

Machine learning (ML) and artificial intelligence (AI) applications are pivotal in contemporary information systems but face escalating hardware security threats, notably side-channel leakage jeopardizing private input and model data. Current evaluations of these vulnerabilities often occur post-deployment, resulting in high costs and risks. Addressing this gap, we present a novel hardware security simulation framework designed to proactively identify and quantify side-channel leaks attributable to processor instructions and stages. Our framework also facilitates root-cause analysis at the register-transfer level (RTL)-stage pre-silicon level, enabling early detection and mitigation of vulnerabilities within ML system designs. To validate our framework’s effectiveness, we conducted a case study evaluating the security of a RISC-V based FPGA implementation of an ML application during its early design phase, comparing simulated leakage against real hardware performance. Our results indicate that our pre-silicon tests detect vulnerabilities with $0.25 \times$ fewer traces compared to traditional post-silicon methods, underscoring the framework’s capability to comprehensively assess and defend against hardware-based attacks prior to deployment. Additionally, through root-cause analysis, we demonstrate which processor stages and units are more leaky, enabling targeted countermeasures early in the design process.