Data Remanence Vulnerabilities in Commercial SRAM at Low Temperature

This paper presents an in-depth analysis of data remanence vulnerabilities in both embedded and standalone Static Random-Access Memory (SRAM). We demonstrate a data remanence attack that leverages prolonged Data Remanence Time (DRT) in low-temperature environments. Our experimental results show nearly perfect data retention of almost $100 \%$ for up to 600 milliseconds at -25°C for known images, highlighting the real-world implications of this phenomenon for predicting and mitigating SRAM-based security risks. Finally, we develop a conceptual framework as part of our root cause analysis, linking leakage current behavior to DRT, enabling predictive modeling of DRT.