Vertically integrated security devices with physically unclonable function and random number generation

Physically unclonable function (PUF) and random number generation (RNG) are commonly used security tools to protect sensitive information from external threats. This paper presents an approach to implement these tools based on three-dimensional monolithic and vertical integration, combining an overlying transistor for the PUF with an underlying transistor for RNG. The PUF was implemented using a polycrystalline silicon (poly-Si) thin-film transistor (TFT), while RNG was realized with a single crystalline silicon (sc-Si) field-effect transistor (FET). The poly-Si TFT for the PUF generates random keys across multiple devices, exhibiting variation of the threshold voltage due to different grain sizes and boundaries. This approach effectively doubles the encryption key capability by creating mirror bits in the source and drain of the poly-Si TFT. The sc-Si FET for RNG produces random numbers due to the stochastic behavior of iterative single transistor latching and unlatching, passing 15 NIST randomness tests. Integrating both security functions into a single chip can significantly reduce resource overhead in terms of hardware footprint and energy consumption, which is crucial in the era of mobile devices, edge computing, autonomous driving, and the Internet of Things.