Energy-Efficient Reconfigurable Acceleration Engine for Polynomial Coefficient Generation of Lattice-Based Post-Quantum Cryptography

Aiming at the problem of energy-efficient design of polynomial coefficient generation algorithms and reconfigurable units in lattice-based post-quantum cryptography, this paper investigates and implements an efficient coefficient generation acceleration engine for multiple algorithms. In this paper, we investigate discrete Gaussian sampling-based and hash function-based coefficient generation schemes separately. For the schemes based on discrete Gaussian sampling, we propose a reconfigurable discrete Gaussian sampling algorithm utilizing a fusion tree structure, which offers greater flexibility in the random number compression through data extraction, and separates the initial sampling from the correction process, thereby achieving high energy efficiency in a parallel architecture. For those based on hash functions, we propose an energy-efficient parallel algorithm for the generation of reconfigurable coefficients, which could be adapted to a variety of uniform, reject, binomial, and ternary sampling schemes. This algorithm makes effective use of the common arithmetic process for all types of sampling schemes and introduces a data allocation process to improve the efficiency of smaller parameter operations, which provides the basis for an energy-efficient design of the hardware architecture. Building upon these two algorithms, we propose a reconfigurable lattice-based post-quantum cryptographic coefficient generation acceleration engine by investigating the algorithm’s core arithmetic parallelism with the goal of resource efficiency. Experimental results showed that under the 40 nm CMOS process, it takes only 256.2 ns on average to complete the uniform-reject sampling with 256 points rejection value less than 216, and 214.2 ns on average to complete the binomial sampling with 256 points rejection value less than 8 bits. The maximum operating frequency reached 714 MHz, with an average power consumption of approximately 57.37 mW. Compared to existing studies, the proposed sampler reduced power consumption by about 13% for binomial sampling and about 21% for discrete Gaussian sampling.