Novel Design of EXOR Gate and its Application for Circuits using QCA Nanotechnology

Background: QCA nanotechnology is an emerging technology in the current scenario to develop the digital circuits for area-efficient, energy-efficient, low-power, and high-speed applications. The EXOR gate is broadly used in many digital applications. Therefore, an EXOR gate needs to be designed in an emerging technology to tackle the issues of the nanoscale regime of conventional metal oxide semiconductor (MOS) technology. Aim: This study aims to implement an efficient 3-input exclusive OR (EXOR) gate using quantumdot cellular automata (QCA) nanotechnology and check its performance for subsequent circuits. Objective: The objective of this research work is to develop an efficient translation-based 3-input EXOR gate in QCA nanotechnology. The subsequent circuits are designed using the proposed EXOR gate to evaluate the efficacy of extension work. Method: A unique feature of QCA nanotechnology is utilized for the design of the EXOR gate. The translation-based approach is applied for the implementation of the proposed EXOR gate. A QCA cell may be shifted from its initial position in order to form the logic function. The translation-based method saves the area requirement. Result: The proposed EXOR gate consists of only 10 QCA cells and 0.50 clocks. The energy dissipation and fault analyses are done for the proposed EXOR gate. A thorough comparative study is prepared for the performance evaluation. The various subsequent circuits, such as a full adder, a 4-bit parity checker, and a 4-bit binary to gray (BTG) code converter, are also designed using the proposed EXOR gate in order to check the extension work on the proposed EXOR gate. Conclusion: It is observed from the simulation work on the proposed EXOR gate that it saves layout area and is most cost-effective. It is highly optimized in terms of cell count and clock. The proposed EXOR gate saves 25% cell area and 23.08% design cost as compared to the best-reported design. The designed subsequent circuits also outperform in terms of different parameters. The full adder reduces 33.33% cell count and 34.85% cost as compared to the best-reported design. The 4- bit parity checker improves the cell count by 47.50% and the design cost by 57.29% as compared to the best-reported work. The 4-bit BTG code converter minimizes layout area by 25.81% and design cost by 29.30% as compared to the best-reported work.