Optimization of digital transistors for low-cost and low-power IoT applications in 40nm technology

The semiconductor industry roadmap primarily focuses on shrinking transistor’s sizes and increasing transistor’s density. Smaller transistors enable faster switching speeds and lower power consumption, contributing to higher operating frequencies. For digital circuits, CMOS devices are designed with a focus on their speed, which is a critical parameter for high performance applications. Nevertheless, for IoT (Internet of Things) applications, the requirements are quite different as CMOS devices are designed to balance various parameters including speed and power consumption. In this context, this paper proposes to optimize the energy efficiency of CMOS transistors by adjusting the supply voltage while ensuring an acceptable operating frequency. A 40 nm Embedded Non-Volatile Memory (eNVM) technology is considered and three MOS transistors with different threshold voltages (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>) are evaluated. Transistor-level as well as circuit-level measurement and simulation results are proposed to find an optimal power consumption with respect to the minimal operating frequency, considering each transistor flavor. We have shown that it is possible to reduce the supply voltage of a digital circuit by up to 35%, leading to a power consumption reduction of 50%, at zero-cost by selecting the right transistor flavor.