Punch-through variability in buried channel transistors
In this study, we present experimental findings regarding the variability observed in transistors employing a buried channel. In weak inversion regime this arsenic implantation plays the role to adjust the threshold voltage. A set of 1D simulations is used to show the impact on current-voltage characteristics. A correlation between the leakage current and the spatial position on a 300mm wafer has been considered, as well as a Principal Component Analysis. The objective is to understand the factors contributing to this variability.
Authors
- M. Mantelli
- A. Regnier
- V. Della Marca (ORCID: https://orcid.org/0000-0003-3761-8122)
- Thibault Kempf
- Pascal Le Masson (ORCID: https://orcid.org/0000-0002-3835-2875)
- S. Niel
- Radouane Habhab (ORCID: https://orcid.org/0009-0001-4640-7709)
- Nadia Miridi
- P. Canet
- J-M. Portal
- S.D. Perrin
- C. Belabbas
Institutions
- Centre National de la Recherche Scientifique (FR)
- Université de Toulon (FR)
- Université Côte d'Azur (FR)
- STMicroelectronics (France) (FR)
- Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (FR)
Publication Details
- Published
- 2024-10-14
- DOI
- https://doi.org/10.1109/dttis62212.2024.10780055
- Citations
- 2
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.42